1. Field of Invention
The present invention relates to a method and circuit thereof for signal sampling/holding, and more particularly, to a method of signal sampling/holding for lowering sampling noise.
2. Description of the Related Art
Signal sampling/holding is one of the major issues of electronic circuits. In order to capture signal characteristics efficiently, a proper signal sampling/holding is exerted. Taking an image sensor as an example, a signal sampling/holding circuit serves to sample and hold an image sensing signal precisely for further processing in back-end circuits. Increasing electronic products are featured with built-in video capturing function, for example, mobile phones, PDA and toys, etc. In order to be adapted to various requirements, especially portable electronic devices, an image sensor with lower power consumption and high resolution is desirable.
Referring to FIG. 1A, it illustrates a block diagram of a conventional image sensor. In FIG. 1A, the conventional image sensor comprises a pixel array 110, a row driver and a voltage reference 120, a sample and hold charge mode readout circuit 130, a gain stage 140 and an A/D converter 150. The row driver and voltage reference 120 provides a reference voltage VCL for each of the row driving signals 121 and the reference voltages 122. Each row electrode (not shown) of the pixel array 110 respectively receives a corresponding row driving signal 121, and the pixel array senses outputs column pixel signals 111 according to a timing signal of the row driving signal 121 after image is sensed by the pixel array 110. The sample and hold charge mode read out circuit 130 simultaneously receives, samples and holds each of the column pixel signals 111, and outputs the pixel signal 131 in cascade manner in response to the pixel signals. The gain stage 140 receives and amplifiers the pixel signal 131 and generates pixel signal 141. The A/D converter 150 is an A/D converter, e.g. a pipeline A/D converter, converting the analog pixel signals 141 into digital pixel signal 151 in response to the reference voltage 122, for further processing with the back-end circuits, e.g. a control logic 160 in this image sensor.
In the sample and hold charge mode readout circuit 130 of the image sensor, a pixel signal is captured to a sampling device (e.g. a capacitor) via a sampling switch. The charges that cause noise is transferred to the signal that is sampled during switching off the sampling switch, which is referred to random signal noise to the image, and image quality is thus lowered. Since the sampling switch noise of the pixel signal is randomly generated, it is hardly filtered out in the back-end circuits. For description purpose, a CMOS image sensor is illustrated as an example hereinafter. Referring to FIG. 1B, it illustrates a schematic circuit diagram of a sample and hold column circuit of a CMOS image sensor. For depicting purpose, one of the pixels in the pixel array is illustrated as a pixel 112 in FIG. 1B. Moreover, the sample and hold column circuit comprises a plurality of sample/hold circuits, wherein one circuit is illustrated as an example.
Referring to FIG. 1C, it illustrates a temporal waveform diagram of signals of the sample and hold circuit of the CMOS image sensor in FIG. 1B. Referring to FIGS. 1B and 1C, a CMOS image sensor requires a sampled pixel signal value and a sampled reset signal value, whereas a reference voltage VCL is required for sampling reference. A gate of a signal follower sf is coupled to a cathode of a photo diode PD. During period A for sampling pixel signal value, control signals row_en, clamp and samp_sig are switched to high logic level, whereas control signals rst_en, samp_rst, cb and col_addr are switched to low logic level. The photo diode PD is radiated by light, such that a reverse bias potential across the two terminals of the photo diode PD are lowered correspondingly, and a potential difference between the pixel signal value outputted via the signal follower sf and the reference voltage VCL is stored in the capacitor CS1. During period B for sampling reset signal value, the control signals row_en, rst_en, clamp and samp_rst are switched to high logic level, whereas the control signals samp_sig, cb and col_addr are switched to low logic level. Where the cathode of the photo diode PD is re-coupled to the system potential Vaa, from which a corresponding reset signal value of the signal follower sf is outputted. A potential difference between the reset signal value and the reference voltage VCL is thus stored in the capacitor CS2.
After pixel signal is sampled, the control signals samp_sig and samp_rst are switched to low logic level, and a sensing switch of the control signal clamp is switched off before entering period C for signal value holding. During period C for signal value holding, each of row pixel signals 111 is respectively held in one of the corresponding sample/hold circuits, where each of the sample/hold circuits sequentially switches on the sensing switches controlled by the control signals cb and col_addr in response to a timing signal, and pixel signals (including the pixel signal value and the reset signal value) 131 is outputted in sequence to the gain stage 140.
When period A for sampling pixel signal value is terminated, the sensing switch is turned off by the control signal samp_sig, i.e., the sensing switch is changed from on status to off status, an inevitable problem occurs. That is, the charges are distributed randomly along the sensing switch, and thus are transferred to the sampled pixel signal value as random noise. Moreover, before period B for sampling reset signal value is terminated, the sensing switch is turned off by the control signal samp_sig, i.e., the sensing switch is changed from open status to off status, an inevitable problem as well occurs. That is, the charges are distributed randomly along the sensing switch, and thus are transferred to the sampled pixel signal value as random noise. The foregoing random noise is referred as front-end noise of the data path, which is hardly filtered out by back-end circuits. When the pixel signal is amplified, the random noise is as well amplified with the pixel signal, thus a signal over noise ratio (S/N ratio) is lowered as well as image quality.